The integrated circuit industry has, since its inception, maintained a remarkable growth rate by driving increased device functionality at lower cost. One of the primary enabling factors of this growth has been the ability of optical lithography to steadily decrease the smallest feature size that can be formed as part of the integrated circuit pattern. The steady decline in feature size and cost and the corresponding increase in the density of features printed per circuit are commonly referred to as “Moore's Law” or the lithography “roadmap.”
The lithography process involves creating a master image on a mask or reticle (mask and reticle are used interchangeably herein), then projecting an image from the mask onto a resist-covered semiconductor wafer in order to create a pattern that matches the design intent of defining functional elements, such as transistor gates, contacts etc., on the wafer. The more times a master pattern is successfully replicated on a wafer within the design specifications, the lower the cost per finished device or “chip” will be. Until recently, the mask pattern has been an almost exact duplicate of the desired pattern at the wafer level, with the exception that the mask level pattern may be several times larger than the wafer level pattern, due to an imaging reduction ratio of the exposure tool. The mask is typically formed by depositing and patterning a light absorbing material on quartz or another transparent substrate. The mask is then placed in an exposure tool known as a “stepper” or “scanner” where light of a specific exposure wavelength is directed through the mask onto the wafers. The light is transmitted through clear areas of the mask, but is attenuated by a desired amount, typically between 90 and 100%, in the areas covered by the absorbing layer. The light that passes through some regions of the mask may also be phase shifted by a desired phase angle, typically an integer multiple of 180 degrees. After being collected by the projection optics of the exposure tool, the resulting aerial image pattern is then focused onto the wafers. A light-sensitive material (photoresist or resist) deposited on the wafer surface interacts with the light to form the desired pattern on the wafer, and the pattern is then transferred into the underlying layers on the wafer to form functional electrical circuits according to well-known processes.
In recent years, the feature sizes being patterned have become significantly smaller than the wavelength of light used to transfer the mask pattern onto the wafer. This trend towards “sub-wavelength lithography” has resulted in increasing difficulty in maintaining adequate process margins in the lithography process. The aerial images created by the mask and exposure tool lose contrast and sharpness as the ratio of feature size to wavelength decreases. This ratio is quantified by the k1 factor, defined as the numerical aperture (NA) of the exposure tool times the minimum feature size Wf divided by the wavelength λ, i.e., k1=NA·Wf/λ. There is limited practical flexibility in choosing the exposure wavelength, while the numerical aperture of exposure tools is approaching physical limits. Consequently, the continuous reduction in device feature sizes requires more and more aggressive reduction of the k1 factor in lithographic processes, i.e. imaging at or below the classical resolution limits of an optical imaging system.
New methods to enable low-k1 lithography have used master patterns on the mask that are no longer exact copies of the final wafer level pattern. The mask pattern is often adjusted in terms of the size and placement of pattern features as a function of pattern density or pitch. Other techniques involve the addition or subtraction of extra corners on the mask pattern (“serifs,” “hammerheads,” and other patterns) known as Optical Proximity Correction, or OPC; and the addition of other geometries that are not intended to be replicated on the wafer at all. The sole purpose of these non-printing “assist features,” also known as Sub-Resolution Assisting Features (SRAFs) or scattering bars, is to enhance the printability of the “main features.” The SRAFs are typically small bars placed close to the main features so that the printability of the main features is more robust against focus and/or dose change. All of these methods are often referred to collectively as Resolution Enhancement Technology (RET). With decreasing k1, the magnitude of proximity effects increases dramatically. In current high-end designs, more and more device layers require RET, and almost every feature edge requires some amount of adjustment to ensure that the printed pattern will reasonably resemble the design intent. The implementation and verification of such extensive RET application is only made possible by detailed full-chip computational lithography process modeling, and the process is generally referred to as model-based RET. (See “Full-Chip Lithography Simulation and Design Analysis—How OPC Is Changing IC Design,” C. Spence, Proc. SPIE, Vol. 5751, pp. 1-14 (2005) and “Exploring New High Speed, Mask Aware RET Verification Flows,” P. Martin et al., Proc. SPIE 5853, pp. 114-123, (2005)).
The cost of manufacturing advanced mask sets is steadily increasing. Currently, the cost has already exceeded one million dollars per mask set for an advanced device. In addition, the turn-around time is always a critical concern. As a result, lithography-driven RET design, which assists in reducing both the cost and turn-around time, has become an integral part of semiconductor manufacturing.
FIG. 1 is a flowchart of a prior art method for applying resolution enhancement techniques to a design layout. In step 110, a design layout that describes the shapes and sizes of patterns that correspond to functional elements of a semiconductor device, such as diffusion layers, metal traces, contacts, and gates of field-effect transistors, is obtained. These patterns represent the “design intent” of physical shapes and sizes that need to be reproduced on a wafer by the lithography process in order to achieve certain electrical functionality and specifications of the final device. The design layout is also referred to as the “pre-RET” layout.
As described above, numerous modifications to this design layout are required to create the patterns on the mask or reticle used to print the desired structures. In step 112, a variety of RET methods are applied to the design layout in order to approximate the design intent in the actually printed patterns. The resulting “post-RET” mask layout differs significantly from the “pre-RET” design layout. Both the Pre- and Post-RET layouts may be provided to the lithography simulation system in a polygon-based hierarchical data file in, e.g., the GDS or the OASIS format.
In step 114, resist contours on the wafer are simulated using the post-RET layout and a model of the lithography process. This model includes an optical model component that describes the transformation from the post-RET layout to an aerial image (AI) and a resist model component that describes the transformation from the AI to the final resist image (RI). In step 116, the simulated resist contours are extracted from the RI and compared to the design layout, and in step 118 its is determined whether the simulated resist contours are acceptable. If they are not acceptable, then the method returns to step 112 where another iteration of RET methods are applied to the pre-RET layout. If the simulated resist contours are acceptable, then the post-RET layout is output and used to manufacture a mask.
A central part of lithography simulation is the optical model component of the model of the lithography process, which simulates the projection and image forming process in the exposure tool. The optical model needs to incorporate critical parameters of the illumination and projection system: numerical aperture and partial coherence settings, illumination wavelength, illuminator source shape, and possibly imperfections of the system such as aberrations or flare. The projection system and various optical effects, e.g., high-NA diffraction, scalar or vector, polarization, and thin-film multiple reflection, may be modeled by transmission cross coefficients (TCCs). The TCCs may be decomposed into convolution kernels, using an eigen-series expansion. For computation speed, the series is usually truncated based on the ranking of eigen-values, resulting in a finite set of kernels. The more kernels that are kept, the less error is introduced by the truncation. The lithography simulation system described in U.S. Pat. No. 7,003,758 allows for optical simulations using a very large number of convolution kernels without negative impact on computation time and therefore enables highly accurate optical modeling. (See “Optimized Hardware and Software for Fast, Full Chip Simulation,” Y. Cao et al., Proc. SPIE Vol. 5754, 407 (2005)).
As the lithography process entered below the 65 nm node, leading-edge chip designs have minimum feature sizes smaller than the wavelength of light used in advanced exposure tools. SRAFs become indispensable even if OPC techniques provide good results. Typically, OPC will modify the design layout so that a resist image (RI) contour is close enough to the design target at nominal condition. However, the Process Window (PW) is rather small without any extra features. SRAFs are needed to enhance the printability of the main features across a wider range of defocus and delta dose scenarios in order to maintain adequate process margins in the lithography process.
One method for implementing SRAFs that is widely in use is rule-based SRAF placement using an empirical (manual) rule-generator. In this method, a combination of benchmark test patterns with different SRAF configurations are printed (or simulated) on a wafer. Critical Dimension (CD) is then measured on the wafer, a set of rules for SRAF placement is drawn from the CD comparison, and finally the set of rules is used in SRAF placement for each main feature segment in a design. It should be noted that empirical rule-based SRAF placement requires an efficient mechanism to solve many conflicts between SRAFs derived from different main feature segments.
Another proposed method to generate SRAFs is based on inverse lithography techniques. In this method, the goal is to identify a mask image that minimizes an objective function. The objective function includes the difference between the resulting aerial image and the ideal design target image and also the difference between the aerial image intensity at the design target edge locations and the threshold for contours. To solve this non-linear programming problem, two iterative approaches are proposed to identify a local minimum solution. In the first approach, referred to as “local variations algorithm,” each pixel in the mask layout is added with a hypothetical disturbance, and the resulting objective function value is compared against the one without the disturbance to decide whether this disturbance should be added or not. After all the pixels are processed in such a way, the whole process is iterated with smaller and smaller disturbances until the disturbance is small enough (thus the mask image will not change much after more iterations). In the second approach, referred to as “gradient descent algorithm,” the gradient of the objective function is computed and the non-linear problem is replaced by its linear approximation. Then the linear approximation is solved iteratively until certain convergence criteria are met. (see “Dense OPC for 65 nm and below,” N. B. Cobb and Y. Granik, Proc. of SPIE, Vol. 5992, pp. 1521-1532, (2005)).
While these method have demonstrated some successes, their disadvantages have slowed the development cycle and limited their usage. For example, the empirical (manual) rule-generator has the following drawbacks: unable to take into account all possible patterns/spaces/line widths in a limited number of test patterns; high cost and low speed to manufacture the mask, print the wafer, and measure CD; difficulty in measuring the SRAFs' performance across the PW; and difficulty in resolving SRAF conflicts. The inverse lithography based method is also complicated and slow, since it may require quite a few slow iterations to converge. It may also converge to a local optimum, and it is not feasible to use it directly as it generates continuous values for each pixel while only rectangular shaped patterns with mask constraints are manufacturable. In addition, the objective function includes the difference between the whole aerial image and the design target, while in practice, the fidelity of the aerial image contours is of more interest. The focus on pixels deep inside or outside main features may be counterproductive. As a result, there exists a strong need for methods to create a very fast and very efficient SRAF placement algorithm that will take 2D pattern shapes into consideration and optimize for the PW rather than a few test patterns.